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<span id="IA_002d64-Options"></span><div class="header">
<p>
Next: <a href="LM32-Options.html" accesskey="n" rel="next">LM32 Options</a>, Previous: <a href="HPPA-Options.html" accesskey="p" rel="prev">HPPA Options</a>, Up: <a href="Submodel-Options.html" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html" title="Index" rel="index">Index</a>]</p>
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<hr>
<span id="IA_002d64-Options-1"></span><h4 class="subsection">3.19.20 IA-64 Options</h4>
<span id="index-IA_002d64-Options"></span>

<p>These are the &lsquo;<samp>-m</samp>&rsquo; options defined for the Intel IA-64 architecture.
</p>
<dl compact="compact">
<dd><span id="index-mbig_002dendian-6"></span>
</dd>
<dt><code>-mbig-endian</code></dt>
<dd><p>Generate code for a big-endian target.  This is the default for HP-UX.
</p>
<span id="index-mlittle_002dendian-6"></span>
</dd>
<dt><code>-mlittle-endian</code></dt>
<dd><p>Generate code for a little-endian target.  This is the default for AIX5
and GNU/Linux.
</p>
<span id="index-mgnu_002das"></span>
<span id="index-mno_002dgnu_002das"></span>
</dd>
<dt><code>-mgnu-as</code></dt>
<dt><code>-mno-gnu-as</code></dt>
<dd><p>Generate (or don&rsquo;t) code for the GNU assembler.  This is the default.
</p>
<span id="index-mgnu_002dld-1"></span>
<span id="index-mno_002dgnu_002dld"></span>
</dd>
<dt><code>-mgnu-ld</code></dt>
<dt><code>-mno-gnu-ld</code></dt>
<dd><p>Generate (or don&rsquo;t) code for the GNU linker.  This is the default.
</p>
<span id="index-mno_002dpic"></span>
</dd>
<dt><code>-mno-pic</code></dt>
<dd><p>Generate code that does not use a global pointer register.  The result
is not position independent code, and violates the IA-64 ABI.
</p>
<span id="index-mvolatile_002dasm_002dstop"></span>
<span id="index-mno_002dvolatile_002dasm_002dstop"></span>
</dd>
<dt><code>-mvolatile-asm-stop</code></dt>
<dt><code>-mno-volatile-asm-stop</code></dt>
<dd><p>Generate (or don&rsquo;t) a stop bit immediately before and after volatile asm
statements.
</p>
<span id="index-mregister_002dnames"></span>
<span id="index-mno_002dregister_002dnames"></span>
</dd>
<dt><code>-mregister-names</code></dt>
<dt><code>-mno-register-names</code></dt>
<dd><p>Generate (or don&rsquo;t) &lsquo;<samp>in</samp>&rsquo;, &lsquo;<samp>loc</samp>&rsquo;, and &lsquo;<samp>out</samp>&rsquo; register names for
the stacked registers.  This may make assembler output more readable.
</p>
<span id="index-mno_002dsdata-1"></span>
<span id="index-msdata-1"></span>
</dd>
<dt><code>-mno-sdata</code></dt>
<dt><code>-msdata</code></dt>
<dd><p>Disable (or enable) optimizations that use the small data section.  This may
be useful for working around optimizer bugs.
</p>
<span id="index-mconstant_002dgp"></span>
</dd>
<dt><code>-mconstant-gp</code></dt>
<dd><p>Generate code that uses a single constant global pointer value.  This is
useful when compiling kernel code.
</p>
<span id="index-mauto_002dpic"></span>
</dd>
<dt><code>-mauto-pic</code></dt>
<dd><p>Generate code that is self-relocatable.  This implies <samp>-mconstant-gp</samp>.
This is useful when compiling firmware code.
</p>
<span id="index-minline_002dfloat_002ddivide_002dmin_002dlatency"></span>
</dd>
<dt><code>-minline-float-divide-min-latency</code></dt>
<dd><p>Generate code for inline divides of floating-point values
using the minimum latency algorithm.
</p>
<span id="index-minline_002dfloat_002ddivide_002dmax_002dthroughput"></span>
</dd>
<dt><code>-minline-float-divide-max-throughput</code></dt>
<dd><p>Generate code for inline divides of floating-point values
using the maximum throughput algorithm.
</p>
<span id="index-mno_002dinline_002dfloat_002ddivide"></span>
</dd>
<dt><code>-mno-inline-float-divide</code></dt>
<dd><p>Do not generate inline code for divides of floating-point values.
</p>
<span id="index-minline_002dint_002ddivide_002dmin_002dlatency"></span>
</dd>
<dt><code>-minline-int-divide-min-latency</code></dt>
<dd><p>Generate code for inline divides of integer values
using the minimum latency algorithm.
</p>
<span id="index-minline_002dint_002ddivide_002dmax_002dthroughput"></span>
</dd>
<dt><code>-minline-int-divide-max-throughput</code></dt>
<dd><p>Generate code for inline divides of integer values
using the maximum throughput algorithm.
</p>
<span id="index-mno_002dinline_002dint_002ddivide"></span>
<span id="index-minline_002dint_002ddivide"></span>
</dd>
<dt><code>-mno-inline-int-divide</code></dt>
<dd><p>Do not generate inline code for divides of integer values.
</p>
<span id="index-minline_002dsqrt_002dmin_002dlatency"></span>
</dd>
<dt><code>-minline-sqrt-min-latency</code></dt>
<dd><p>Generate code for inline square roots
using the minimum latency algorithm.
</p>
<span id="index-minline_002dsqrt_002dmax_002dthroughput"></span>
</dd>
<dt><code>-minline-sqrt-max-throughput</code></dt>
<dd><p>Generate code for inline square roots
using the maximum throughput algorithm.
</p>
<span id="index-mno_002dinline_002dsqrt"></span>
</dd>
<dt><code>-mno-inline-sqrt</code></dt>
<dd><p>Do not generate inline code for <code>sqrt</code>.
</p>
<span id="index-mfused_002dmadd"></span>
<span id="index-mno_002dfused_002dmadd"></span>
</dd>
<dt><code>-mfused-madd</code></dt>
<dt><code>-mno-fused-madd</code></dt>
<dd><p>Do (don&rsquo;t) generate code that uses the fused multiply/add or multiply/subtract
instructions.  The default is to use these instructions.
</p>
<span id="index-mno_002ddwarf2_002dasm"></span>
<span id="index-mdwarf2_002dasm"></span>
</dd>
<dt><code>-mno-dwarf2-asm</code></dt>
<dt><code>-mdwarf2-asm</code></dt>
<dd><p>Don&rsquo;t (or do) generate assembler code for the DWARF line number debugging
info.  This may be useful when not using the GNU assembler.
</p>
<span id="index-mearly_002dstop_002dbits"></span>
<span id="index-mno_002dearly_002dstop_002dbits"></span>
</dd>
<dt><code>-mearly-stop-bits</code></dt>
<dt><code>-mno-early-stop-bits</code></dt>
<dd><p>Allow stop bits to be placed earlier than immediately preceding the
instruction that triggered the stop bit.  This can improve instruction
scheduling, but does not always do so.
</p>
<span id="index-mfixed_002drange-1"></span>
</dd>
<dt><code>-mfixed-range=<var>register-range</var></code></dt>
<dd><p>Generate code treating the given register range as fixed registers.
A fixed register is one that the register allocator cannot use.  This is
useful when compiling kernel code.  A register range is specified as
two registers separated by a dash.  Multiple register ranges can be
specified separated by a comma.
</p>
<span id="index-mtls_002dsize-1"></span>
</dd>
<dt><code>-mtls-size=<var>tls-size</var></code></dt>
<dd><p>Specify bit size of immediate TLS offsets.  Valid values are 14, 22, and
64.
</p>
<span id="index-mtune-7"></span>
</dd>
<dt><code>-mtune=<var>cpu-type</var></code></dt>
<dd><p>Tune the instruction scheduling for a particular CPU, Valid values are
&lsquo;<samp>itanium</samp>&rsquo;, &lsquo;<samp>itanium1</samp>&rsquo;, &lsquo;<samp>merced</samp>&rsquo;, &lsquo;<samp>itanium2</samp>&rsquo;,
and &lsquo;<samp>mckinley</samp>&rsquo;.
</p>
<span id="index-milp32"></span>
<span id="index-mlp64"></span>
</dd>
<dt><code>-milp32</code></dt>
<dt><code>-mlp64</code></dt>
<dd><p>Generate code for a 32-bit or 64-bit environment.
The 32-bit environment sets int, long and pointer to 32 bits.
The 64-bit environment sets int to 32 bits and long and pointer
to 64 bits.  These are HP-UX specific flags.
</p>
<span id="index-mno_002dsched_002dbr_002ddata_002dspec"></span>
<span id="index-msched_002dbr_002ddata_002dspec"></span>
</dd>
<dt><code>-mno-sched-br-data-spec</code></dt>
<dt><code>-msched-br-data-spec</code></dt>
<dd><p>(Dis/En)able data speculative scheduling before reload.
This results in generation of <code>ld.a</code> instructions and
the corresponding check instructions (<code>ld.c</code> / <code>chk.a</code>).
The default setting is disabled.
</p>
<span id="index-msched_002dar_002ddata_002dspec"></span>
<span id="index-mno_002dsched_002dar_002ddata_002dspec"></span>
</dd>
<dt><code>-msched-ar-data-spec</code></dt>
<dt><code>-mno-sched-ar-data-spec</code></dt>
<dd><p>(En/Dis)able data speculative scheduling after reload.
This results in generation of <code>ld.a</code> instructions and
the corresponding check instructions (<code>ld.c</code> / <code>chk.a</code>).
The default setting is enabled.
</p>
<span id="index-mno_002dsched_002dcontrol_002dspec"></span>
<span id="index-msched_002dcontrol_002dspec"></span>
</dd>
<dt><code>-mno-sched-control-spec</code></dt>
<dt><code>-msched-control-spec</code></dt>
<dd><p>(Dis/En)able control speculative scheduling.  This feature is
available only during region scheduling (i.e. before reload).
This results in generation of the <code>ld.s</code> instructions and
the corresponding check instructions <code>chk.s</code>.
The default setting is disabled.
</p>
<span id="index-msched_002dbr_002din_002ddata_002dspec"></span>
<span id="index-mno_002dsched_002dbr_002din_002ddata_002dspec"></span>
</dd>
<dt><code>-msched-br-in-data-spec</code></dt>
<dt><code>-mno-sched-br-in-data-spec</code></dt>
<dd><p>(En/Dis)able speculative scheduling of the instructions that
are dependent on the data speculative loads before reload.
This is effective only with <samp>-msched-br-data-spec</samp> enabled.
The default setting is enabled.
</p>
<span id="index-msched_002dar_002din_002ddata_002dspec"></span>
<span id="index-mno_002dsched_002dar_002din_002ddata_002dspec"></span>
</dd>
<dt><code>-msched-ar-in-data-spec</code></dt>
<dt><code>-mno-sched-ar-in-data-spec</code></dt>
<dd><p>(En/Dis)able speculative scheduling of the instructions that
are dependent on the data speculative loads after reload.
This is effective only with <samp>-msched-ar-data-spec</samp> enabled.
The default setting is enabled.
</p>
<span id="index-msched_002din_002dcontrol_002dspec"></span>
<span id="index-mno_002dsched_002din_002dcontrol_002dspec"></span>
</dd>
<dt><code>-msched-in-control-spec</code></dt>
<dt><code>-mno-sched-in-control-spec</code></dt>
<dd><p>(En/Dis)able speculative scheduling of the instructions that
are dependent on the control speculative loads.
This is effective only with <samp>-msched-control-spec</samp> enabled.
The default setting is enabled.
</p>
<span id="index-mno_002dsched_002dprefer_002dnon_002ddata_002dspec_002dinsns"></span>
<span id="index-msched_002dprefer_002dnon_002ddata_002dspec_002dinsns"></span>
</dd>
<dt><code>-mno-sched-prefer-non-data-spec-insns</code></dt>
<dt><code>-msched-prefer-non-data-spec-insns</code></dt>
<dd><p>If enabled, data-speculative instructions are chosen for schedule
only if there are no other choices at the moment.  This makes
the use of the data speculation much more conservative.
The default setting is disabled.
</p>
<span id="index-mno_002dsched_002dprefer_002dnon_002dcontrol_002dspec_002dinsns"></span>
<span id="index-msched_002dprefer_002dnon_002dcontrol_002dspec_002dinsns"></span>
</dd>
<dt><code>-mno-sched-prefer-non-control-spec-insns</code></dt>
<dt><code>-msched-prefer-non-control-spec-insns</code></dt>
<dd><p>If enabled, control-speculative instructions are chosen for schedule
only if there are no other choices at the moment.  This makes
the use of the control speculation much more conservative.
The default setting is disabled.
</p>
<span id="index-mno_002dsched_002dcount_002dspec_002din_002dcritical_002dpath"></span>
<span id="index-msched_002dcount_002dspec_002din_002dcritical_002dpath"></span>
</dd>
<dt><code>-mno-sched-count-spec-in-critical-path</code></dt>
<dt><code>-msched-count-spec-in-critical-path</code></dt>
<dd><p>If enabled, speculative dependencies are considered during
computation of the instructions priorities.  This makes the use of the
speculation a bit more conservative.
The default setting is disabled.
</p>
<span id="index-msched_002dspec_002dldc"></span>
</dd>
<dt><code>-msched-spec-ldc</code></dt>
<dd><p>Use a simple data speculation check.  This option is on by default.
</p>
<span id="index-msched_002dspec_002dldc-1"></span>
</dd>
<dt><code>-msched-control-spec-ldc</code></dt>
<dd><p>Use a simple check for control speculation.  This option is on by default.
</p>
<span id="index-msched_002dstop_002dbits_002dafter_002devery_002dcycle"></span>
</dd>
<dt><code>-msched-stop-bits-after-every-cycle</code></dt>
<dd><p>Place a stop bit after every cycle when scheduling.  This option is on
by default.
</p>
<span id="index-msched_002dfp_002dmem_002ddeps_002dzero_002dcost"></span>
</dd>
<dt><code>-msched-fp-mem-deps-zero-cost</code></dt>
<dd><p>Assume that floating-point stores and loads are not likely to cause a conflict
when placed into the same instruction group.  This option is disabled by
default.
</p>
<span id="index-msel_002dsched_002ddont_002dcheck_002dcontrol_002dspec"></span>
</dd>
<dt><code>-msel-sched-dont-check-control-spec</code></dt>
<dd><p>Generate checks for control speculation in selective scheduling.
This flag is disabled by default.
</p>
<span id="index-msched_002dmax_002dmemory_002dinsns"></span>
</dd>
<dt><code>-msched-max-memory-insns=<var>max-insns</var></code></dt>
<dd><p>Limit on the number of memory insns per instruction group, giving lower
priority to subsequent memory insns attempting to schedule in the same
instruction group. Frequently useful to prevent cache bank conflicts.
The default value is 1.
</p>
<span id="index-msched_002dmax_002dmemory_002dinsns_002dhard_002dlimit"></span>
</dd>
<dt><code>-msched-max-memory-insns-hard-limit</code></dt>
<dd><p>Makes the limit specified by <samp>msched-max-memory-insns</samp> a hard limit,
disallowing more than that number in an instruction group.
Otherwise, the limit is &ldquo;soft&rdquo;, meaning that non-memory operations
are preferred when the limit is reached, but memory operations may still
be scheduled.
</p>
</dd>
</dl>

<hr>
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